1. Field of the Invention
The present invention is generally related to semiconductor manufacturing, and, more particularly, to advanced process control methodologies for the manufacture of an oxide-nitride-oxide stack of a memory device, and various systems for accomplishing same.
2. Description of the Related Art
Semiconductor manufacturers have increasingly turned to high density flash memory arrays in their integrated circuit design schemes. A flash memory array includes columns of active regions that are separated by columns of insulating field oxide regions. The transistors are spaced apart in the active regions and each row of transistors are bits in a memory word. The transistors are formed with various materials including a type-1 layer of polysilicon, and transistors forming a row in the array are connected by a word-line comprising a type-2 layer of polysilicon.
To achieve a high density integrated circuit, the transistors must be as small as possible. Typically, these high density flash memory integrated circuits utilize NAND-type gates as opposed to NOR-type gates since NAND gates have a considerably higher density than NOR gates. Smaller transistors allow more transistors to be placed on a single substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
These memory devices are used to store ever-increasing amounts of data that is generated or used during the operation of modern consumer devices. The market for such memory devices is very competitive. Manufacturers of such devices are constantly searching for ways to improve product yields, reduce costs and reduce fabrication cycle times. Moreover, there is a constant drive to increase the performance capabilities of such memory devices, such as storage capabilities, erase times, etc.
FIG. 1 is a cross-sectional view of a portion of a memory cell 10. In practice, a memory array may be comprised of thousands of the memory cells 10. A plurality of field isolation regions 19, e.g., so-called field oxide regions, are formed in the substrate 11. These field isolation regions may be trench isolation regions or they may be a grown area of oxide that is formed by a LOCOS process. Each memory cell 10 is formed above an active area 11A of the substrate 11 between adjacent field isolation regions 19. The memory cell 10 is comprised of a gate insulation layer 16, which is sometimes referred to as a tunnel oxide layer, a floating gate electrode 18, a composite inter-poly insulation layer 20, and a control gate electrode 22. The composite inter-poly insulation layer 20 may be comprised of a layer of silicon dioxide 20A, a layer of silicon nitride 20B and a layer of silicon dioxide 20C. Such a combination is sometimes referred to as an oxide-nitride-oxide (ONO) layer or stack. The floating gate electrode 18 and the control gate electrode 22 may be made of, for example, polysilicon.
Many different process steps are employed in manufacturing the portion of the memory cell 10 depicted in FIG. 1. For example, such processes include various deposition steps, various thermal growth processes and various masking and etching operations. Given the continual drive to increase the performance capabilities of such memory cells 10, each aspect of the manufacture of the various portions of the memory cell 10 may have a bearing on the ultimate capabilities of the memory cell 10, as well as integrated circuit products incorporating such memory cells 10. The ability to control the manufacturing process used to form such memory cells 10 so as to produce memory cells 10 meeting desired levels of performance is very desirable.
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.